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EM78P5840N /41N/42N
8-Bit Microcontrollers
Product Specification
Doc. Version 1.0
ELAN MICROELECTRONICS CORP.
April 2006
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Copyright (c) 2006 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
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Contents
Contents
1 2 General Description .................................................................................................. 1 Features ..................................................................................................................... 1 2.1 2.2 2.3 2.4 2.5 3 4 5 6 7 CPU ....................................................................................................................1 Operating Frequency Mode ................................................................................2 PWM ...................................................................................................................2 ADC ....................................................................................................................2 POR ....................................................................................................................2
2.6 Package Type .....................................................................................................2 Applications............................................................................................................... 3 Pin Assignment ......................................................................................................... 3 Pin Description.......................................................................................................... 4 Block Diagram ........................................................................................................... 5 Function Description ................................................................................................ 6 7.1 Register Configuration ........................................................................................6
7.1.1 7.1.2 R Page Register Configuration ...........................................................................6 IOC Page Register Configuration........................................................................7 R0 (Indirect Addressing Register) .......................................................................7 R1 (TCC) .............................................................................................................8 R2 (Program Counter).........................................................................................8 R3 (Status, Page Selection) ................................................................................9 R4 (RAM Selection for Common Registers R20 ~ R3F)...................................10 R5 (Program Page Selection, PWM Control)....................................................10 R6 (Port 6 I/O Data, PWM Control)...................................................................11 R7 (Port 7 I/O Data, ADC, PWM Duty Cycle)....................................................12 R8 (PWM1 Period) ............................................................................................13 R9 (Port 9 I/O Data, DT2L)................................................................................13 RA (PLL, Main Clock Selection, Watchdog Timer, DT2H) ................................14 RB (ADC Input Data Buffer) ..............................................................................16 RC (Port C I/O Data, Counter 1 Data)...............................................................16 RE (Interrupt Flag).............................................................................................17 RF (Interrupt Status)..........................................................................................17 R10~R3F (General Purpose Register)..............................................................18
7.2
Register Operations ............................................................................................7
7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16
Product Specification (V1.0) 04.25.2006
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Contents
7.3
Special Function Registers ...............................................................................18
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 A (Accumulator).................................................................................................18 CONT (Control Register)...................................................................................18 IOC6 (Port 6 I/O Control, P6 Pin Switch Control) .............................................20 IOC7 (Port 7 I/O Control, Port 7 Pull-high Control) ...........................................22 IOC9 (Port 9 I/O Control, Port 9 Switches) .......................................................23 IOCA (Port 9 PMS Switch Control)....................................................................23 IOCB (ADC Control) ..........................................................................................23 IOCC (Port C I/O Control, ADC Control) ...........................................................25 IOCD (Tone 1 Control, Clock Source, CN1 Prescaler) .....................................26 IOCE (Interrupt Mask) .......................................................................................27 IOCF (Interrupt Mask) .......................................................................................28
7.4 7.5 7.6
Instruction Set ...................................................................................................30 Code Option Register .......................................................................................32 I/O Port..............................................................................................................33
7.6.1 7.6.2 I/O Structure ......................................................................................................33 I/O Description...................................................................................................34
7.7 7.8 7.9
Reset.................................................................................................................36 Wake-up............................................................................................................36 Interrupt.............................................................................................................37
7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.10.7 Overview ...........................................................................................................38 Relative Register Description ...........................................................................39 Increment Timer Counter (TMRX: TMR1H/TMR1L or TMR2H/TMR2L) ...........40 PWM Period (PRDX: PRD1 or PRD2) ..............................................................40 PWM Duty Cycle (DTX: DT1H/ DT1L; DTL: DL1H/DL1L) ................................41 PWM Programming Procedure/Steps ...............................................................41 Timer (TMRX)....................................................................................................41
7.10 PWM (Pulse Width Modulation) ........................................................................38
7.11 Oscillator ...........................................................................................................43
7.11.1 Crystal Mode .....................................................................................................43 7.11.2 IRC Mode ..........................................................................................................44 7.11.3 ERIC Mode........................................................................................................44
7.12 Power-on Considerations..................................................................................46 8 9 10 7.13 External Power-on Reset Circuit.......................................................................46 Absolute Maximum Ratings ................................................................................... 48 DC Electrical Characteristics ................................................................................. 48 9.1 Device Characteristic Graphics.........................................................................49 AC Electrical Characteristics ................................................................................. 50 10.1 Operating Voltage vs Main CLK........................................................................51 11 12 10.2 10-Bit ADC Characteristics ...............................................................................52 Timing Diagrams ..................................................................................................... 53 OTP ROM Burning Pins .......................................................................................... 54
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Product Specification (V1.0) 04.25.2006
Contents
APPENDIX
A B Package Type........................................................................................................... 55 Package Information............................................................................................... 55 B.1 B.2 B.3 B.4 B.5 B.6 C D EM78P5840NM.................................................................................................55 EM78P5840NP .................................................................................................56 EM78P5841NM.................................................................................................56 EM78P5841NP .................................................................................................57 EM78P5842NM.................................................................................................57 EM78P5842NP .................................................................................................58
B.7 EM78P5842NK .................................................................................................58 Numbering System ................................................................................................. 59 EM78P5840N Series ................................................................................................ 59 D.1 D.2 EM78P5840N Series Category.........................................................................59
D.1.1 D.2.1 Differences between ICE5840, EM78P5840N and EM785840N......................59 Differences between EM78P5840N, EM78P5841N, and EM78P5842N..........60
EM78P5840N Series Package Type.................................................................59
E
Application Notes.................................................................................................... 61
Product Specification (V1.0) 04.25.2006
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Contents
Specification Revision History
Doc. Version 1.0 Initial version Revision Description Date 2006/04/25
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Product Specification (V1.0) 04.25.2006
EM78P5840N/41N/42N
8-Bit Microcontrollers
1
General Description
The EM78P5840N/41N/42N series are 8-bit RISC architecture microcontroller devices designed and developed with low-power, high-speed CMOS technology. Each of these devices has on-chip 4Kx13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user's OTP memory code as well as from unwanted external accesses. A number of one-time programmable option bits are also available to meet user's application requirements. Functional flexibility of these integrated ICs is enhanced with their internal special features such as watchdog timer (WDT), program OTP-ROM, RAM, programmable real-time clock/counter, internal interrupt, power down mode, dual PWM (Pulse Width Modulation), 8-channel 10-bit A/D converter, and tri-state I/O.
NOTE Refer to the Application Notes provided in the Appendix for important reminders before using the microcontroller described herein. Convention on tables used to describe register attributes (bit number, bit name, type, etc.), are also provided in the Appendix.
2
Features
2.1 CPU
Operating voltage: 2.2V~5.5V at the main CLK (less than 3.58MHz) Main CLK fSYS < 3.58MHz: 2.2V Main CLK fSYS = 14.3MHz: 3.6V IRC mode: 4MHz, 2MHz Voltage deviation: 5% (2.3V~5.5V) Process deviation: Typ. 3%, Max. 5% Temperature deviation: 5% (-40C~85C) 4K x 13 OTP-ROM 144 x 8 general propose RAM 19 bi-directional and three input-only general purpose I/O 8-level stack for subroutine nesting 8-bit real time clock/counter (TCC) One 8-bit counter interrupt On-chip watchdog timer (WDT) Single-instruction cycle commands
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EM78P5840N/41N/42N
8-Bit Microcontrollers
Three operation modes using crystal oscillator (Main clock can be programmed to 3.58 MHz or 14.3 MHz):
Mode Sleep Green Normal CPU Status Off On On Main Clock Off Off On 32.768kHz Clock Status Off On On
Two Normal mode frequency levels: 3.58 MHz and 14.3 MHz Input port interrupt function Dual-clock operation (Internal PLL main clock, External 32.768kHz)
2.2
Operating Frequency Mode
Crystal mode (the XIN and XOUT pins are connected to the external crystal and capacitor) ERIC mode (the ERCI pin connects the resistor to VDD) IRC mode
2.3
PWM
Dual PWM (Pulse Width Modulation) with 10-bit resolution Programmable period (or baud rate) Programmable duty cycle
2.4
ADC
Operating voltage: 2.5V5.5V
Converter Rate Operating Voltage (min) 74.6K 3.5V 37.4K 3.0V 18.7K 2.5V 9.3K 2.5V
8-channel 10-bit successive approximation A/D converter Internal (VDD) reference voltage
2.5 2.6
POR
Power-on reset
Package Type
EM78P5840NM: 18-pin SOP EM78P5841NM: 20-pin SOP EM78P5842NP: 24-pin PDIP EM78P5840NP: 18-pin PDIP EM78P5841NP: 20-pin PDIP EM78P5842NK: 24-pin Skinny DIP
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Product Specification (V1.0) 04.25.2006
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EM78P5840N/41N/42N
8-Bit Microcontrollers
3
Applications
General purpose I/O product applications A/D applications
4
Pin Assignment
CIN/P94 P95 P96 AVDD /P70/INT0 AVSS AD6/P65 AD5/P64 AD4/P63 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 AD8/P93 AD7/P92 AD2/P91 AD1/P90 INT3/P73 /RESET/P71/INT1 XOUT/P60 XIN/P61 AD3/P62
Figure 4-1a EM78P5840NM & EM78P5840NP
CIN/P94 P95 P96 P97 AVDD /P70/INT0
/P70/INT0
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
AD8/P93 AD7/P92 AD2/P91 AD1/P90 PWM2/PC2 PWM1/PC1 INT3/P73 P74 P75 P76 /RESET/P71/INT1 XOUT/P60
AVSS AD6/P65 AD5/P64
/RESET/P71/INT1 XOUT/P60 XIN/P61
AD4/P63 AD3/P62 XIN/P61
Figure 4-1b EM78P5841NM & EM78P5841NP
Figure 4-1c EM78P5842NM & EM78P5842NP
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(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
5
Pin Description
Pin Name
Power AVDD AVSS Clock XIN XOUT PLLC OSC CIN I O I I I Input pin for the 32.768 kHz oscillator Output pin for the 32.768 kHz oscillator Phase lock loop capacitor. Connect a capacitor (0.047F to 0.1F) to ground ERIC mode clock signal input. This pin is shared with PLLC. Counter 1 external CLK input. This pin is shared with P94. Note that the frequency of the input CLK must be less than 1MHz. ADC Input Channel 1. This pin is shared with Port 90. ADC Input Channel 2. This pin is shared with Port 91. ADC Input Channel 3. This pin is shared with Port 62. ADC Input Channel 4. This pin is shared with Port 63. ADC Input Channel 5. This pin is shared with Port 64. ADC Input Channel 6. This pin is shared with Port 65. ADC Input Channel 7. This pin is shared with Port 92. ADC Input Channel 8. This pin is shared with Port 93. Pulse width modulation output. This pin is shared with Port C1. Pulse width modulation output. This pin is shared with Port C2. Each bit in Port 60 and Port 61 can be an input or output port. These two pins can be used for the ERIC and IRC modes. Each bit in Port 62 to Port 65 can be an input or output port. Each bit in Port 70 can be an input or output port. Port 71 is input only Each bit in Port 7 can be an input or output port. Each bit in Port 9 can be an input or output port. Each bit in Port C can be an input or output port. Interrupt sources. A falling or rising edge signal (controlled by the CONT register) in Port 70 will generate an interrupt. Interrupt sources with the same interrupt flag. A falling edge signal on any pin in Port 71 will generate an interrupt. Interrupt sources with the same interrupt flag. A falling edge signal on any pin in Port 73 will generate an interrupt. Low reset Power supply Ground
I/O
Description
10-Bit 8 Channel A/D AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 PWM PWM1 PWM2 IO P60 ~ P61 P62 ~P65 P70 P71 P73 ~ P76 P90 ~ P97 PC1 ~ PC2 INT0 INT1 INT3 /RESET I/O I/O I/O I I/O I/O I/O (Port 70) (Port 71) Port 73 I O O I I I I I I I I
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EM78P5840N/41N/42N
8-Bit Microcontrollers
6
Block Diagram
CPU Data RAM Control Register
Timing Control
Timer TCC Counter 1 Counter 2 WDT
I/O Port
ROM
PWM 10- bit A/D
Figure 5-1a EM78P5840N/41N/42N Block Diagram
XIN
XOUT
PLLC
WDT timer ROM R2 Stack Prescaler
Oscillator Timing Control
R1 (TCC)
Interrupt Control General RAM
Instruction Register R3 R5 Instruction Decoder
ALU
Control sleep and wakeup on I/O port
ACC
R4
DATA & Control Bus
IOC6 R6 PWM 10-bit A/D Port 6
IOC7 R7 Port 7
IOC9 R9 Port 9
IOCC RC Port C
P60~P61
P62~P65
P71
P70 P73~P76
P90~P97
PC1~PC2
Figure 5-1b EM78P5840N/41N/42N Block Diagram
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7
Function Description
7.1 Register Configuration
7.1.1 R Page Register Configuration
R Page Registers Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F R Page 0 R Page 1 R Page 2 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve Reserve R Page 3 Reserve Reserve Reserve Reserve Reserve PWM Control PWM1 Duty PWM1 Control Duty of PWM1 PWM1 Period PWM2 Duty PWM2 Control PWM2 Duty PWM2 Period Reserve Reserve Reserve Reserve
Indirect addressing Reserve TCC PC Page, Status RAM bank, RSR Reserve Reserve Reserve Reserve
Program ROM page Reserve Port 6 I/O data Port 7 I/O data Reserve Port 9 I/O data PLL, Main clock, WDTE Reserve Port C I/O data Reserve Interrupt flag Interrupt flag Reserve ADC MSB output data Reserve Reserve Reserve ADC output data buffer Counter 1 data Reserve Reserve Reserve
16 bytes Common registers
20 : 3F
Bank 0 Common registers
Bank 1 Common registers
Bank 2 Common registers
Bank 3 Common registers
32x8 for each bank 32x8 for each bank 32x8 for each bank 32x8 for each bank
Addresses 00~0F with Page 0~Page 3 are special registers. Addresses 10~1F are global with general purpose memory. Use the MOV instruction to set the MCU to read data from or write data to these registers directly. This will ignore the RAM bank select bits (RB1, RB0 in R4 Page 0). Addresses 20~3F are general purpose RAM, but the bank number must be indicated before accessing data.
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Product Specification (V1.0) 04.25.2006
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.1.2 IOC Page Register Configuration
IOC Page Registers Addr 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Reserve Reserve Reserve Reserve Reserve Reserve Port 6 I/O control Port 7 I/O control Reserve Port 9 I/O control Reserve Reserve Reserve Reserve Interrupt mask Interrupt mask IOC Page 0 Reserve Reserve Reserve Reserve Reserve Reserve Port 6 switches Port 7 pull high Reserve Reserve Port 9 switches ADC control Reserve Clock source (CN1) Prescaler (CN1) Reserve Reserve IOC Page 1
The IOC registers are special registers. User can use the "IOW" instruction to write data and the "IOR" instruction to read data.
7.2
Register Operations
7.2.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a register actually accesses data pointed by the RAM Select Register (R4). Example: Mov A, @0x20 Mov 0x04, A Mov A, @0xAA Mov 0x00, A
; store an address at R4 for indirect addressing ; write data 0xAA to R20 at Bank0 through R0
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(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.2 R1 (TCC)
The TCC data buffer is Increased by 16.384kHz or by the instruction clock cycle (controlled by the CONT register). It is written and read by the program as with any other register.
7.2.3 R2 (Program Counter)
The R2 structure is depicted in the Figure 7-1 below. The configuration structure generates 4K x 13 external ROM addresses to the corresponding program instruction codes. The "JMP" instruction allows direct loading of the low 10 program counter bits. The "CALL" instruction loads the low 10 bits of the PC, PC+1, and then pushes the data onto the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2, A" allows the loading of an address from the A register to the PC, and the contents of the ninth and tenth bits are cleared to "0.'' "ADD R2,A" allows a relative address to be added to the current PC, and the contents of the ninth and tenth bits are cleared to "0.'' "TBL" allows a relative address to be added to the current PC, and the contents of the ninth and tenth bits don't change. The most significant bit (A10~A11) will be loaded with the contents of bits PS0~PS1 in the status register (R5 Page 0) upon execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction. If an interrupt is triggered, the program ROM will jump to Address 0x08 at Page 0. The CPU will store ACC, the status of R3, and R5 Page automatically; and they will be restored after instruction RETI.
R5 (Page) CALL and Interrupt A11 A10 0 0 0 1 1 0 1 1 A9 A8 A7~A0 RET RETL RETI Stack Stack Stack Stack Stack Stack Stack Stack 1 2 3 4 5 6 7 8 store ACC, R3, R5 (Page) restore
Page 0 00000~003FF Page 1 00400~007FF Page 2 00800~00BFF Page 3 00C00~00FFF
Figure 7-1 Program Counter Organization
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.4 R3 (Status, Page Selection)
(Status Flag, Page Selection Bits)
Bit 7 RPAGE1 R/W-0 Bit 6 R/W-0 Bit 5 R/W-0 Bit 4 T R Bit 3 P R Bit 2 Z R/W Bit 1 DC R/W Bit 0 C R/W
RPAGE0 IOCPAGE
Bit 0 (C): Carry flag Bit 1(DC): Auxiliary carry flag Bit 2 (Z): Zero flag
Bit 3 (P): Power down bit Set to "1" during power on or by a "WDTC" command and reset to "0" by a "SLEP" command. Bit 4 (T): Time-out bit Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
Event WDT wakes up from sleep mode WDT times out (not in sleep mode) /RESET wakes up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 x x = don't care Remarks
Bit 5 (IOCPAGE): Change IOC pages between Page 0 and Page 1 "0" : IOC Page 0 "1" : IOC Page 1 See Section 7.1.2 "IOC Page Register Configuration" for further details. Bits 6~7 (RPAGE0 ~ RPAGE1): Change R pages between Page 0 ~ Page 3
(RPAGE1, RPAGE0) (0, 0) (0, 1) (1, 0) (1, 1) R Page # Selected R Page 0 R Page 1 R Page 2 R Page 3
Refer to Section 7.1.1 "R Page Register Configuration" for further details.
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.5 R4 (RAM Selection for Common Registers R20 ~ R3F)
(RAM Selection Register)
Bit 7 RB1 R/W-0 Bit 6 RB0 R/W-0 Bit 5 RSR5 R/W Bit 4 RSR4 R/W Bit 3 RSR3 R/W Bit 2 RSR2 R/W Bit 1 RSR1 R/W Bit 0 RSR0 R/W
Bit 0 ~ Bit 5 (RSR0 ~ RSR5): Indirect addressing for common Registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1): Bank selection bits for common Registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for the 32 registers (R20 to R3F). Refer to Section 7.1.1 "R Page Register Configuration" for further details.
7.2.6 R5 (Program Page Selection, PWM Control)
Page 0 (Port 5 I/O Data Register, Program Page Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 R/W-0 Bit 2 0 R/W-0 Bit 1 PS1 R/W-0 Bit 0 PS0 R/W-0
Bit 0 ~ Bit 1 (PS0 ~ PS1): Program page selection bits
PS1 0 0 1 1 PS0 0 1 0 1 Program Memory Page (Address) Page 0 Page 1 Page 2 Page 3
The PAGE instruction can be used to maintain the program page. Bit 2 ~ Bit 3 (undefined): These two bits must be set to "0." Otherwise, the MCU will access an incorrect program code. Bit 4 ~ Bit 7 (undefined): not used Page 3 (PWMCON)
Bit 7 PWM2E R/W-0 Bit 6 PWM1E R/W-0 Bit 5 T2EN R/W-0 Bit 4 T1EN R/W-0 Bit 3 T2P1 R/W-0 Bit 2 T2P0 R/W-0 Bit 1 T1P1 R/W-0 Bit 0 T1P0 R/W-0
Bit 0 ~ Bit 1 (T1P0 ~ T1P1): TMR1 clock prescaler option bits
T1P1 0 0 1 1 T1P0 0 1 0 1 Prescaler 1:2 (Default) 1:8 1:32 1:64
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EM78P5840N/41N/42N
8-Bit Microcontrollers Bit 2 ~ Bit 3 (T2P0 ~ T2P1): TMR2 clock prescaler option bits
T2P1 0 0 1 1 T2P0 0 1 0 1 Prescaler 1:2 (Default) 1:8 1:32 1:64
Bit 4 (T1EN): TMR1 enable bit "0" : TMR1 is off (default value) "1" : TMR1 is on Bit 5 (T2EN): TMR2 enable bit "0" : TMR2 is off (default value) "1" : TMR2 is on Bit 6 (PWM1E): PWM1 enable bit "0" : PWM1 is off (default value), and the corresponding pin carries out the PC1 function "1" : PWM1 is on, and the corresponding pin will be automatically set as output pin Bit 7 (PWM2E): PWM2 enable bit "0" : PWM2 is off (default value), and the corresponding pin carries out the PC2 function "1" : PWM2 is on, and the corresponding pin will be automatically set as output pin
7.2.7 R6 (Port 6 I/O Data, PWM Control)
Page 0 (Port 6 I/O Data Register)
Bit 7 Bit 6 Bit 5 P65 R/W Bit 4 P64 R/W Bit 3 P63 R/W Bit 2 P62 R/W Bit 1 P61 R/W Bit 0 P60 R/W
Bit 0 ~ Bit 1 (P60 ~ P61): Ports 60 ~ 61 are used in IRC and ERIC mode. In these modes, Ports 60 ~ 61 are defined as general purpose IO. In Crystal mode, Ports 60 ~ 61 are defined as crystal input (XIN and XOUT) pins. Bit 2 ~ Bit 6 (P62 ~ P65): 4-bit Port 6 I/O data register. The IOC register can be used to set each bit either as input or output. Bit 6 ~ Bit 7 (undefined): These bits are not used Page 3 (DT1L: The Least Significant Byte (Bits 0 ~ 7) of PWM1 Duty Cycle)
Bit 7 PWM1[7] R/W-0 Bit 6 PWM1[6] R/W-0 Bit 5 PWM1[5] R/W-0 Bit 4 PWM1[4] R/W-0 Bit 3 PWM1[3] R/W-0 Bit 2 PWM1[2] R/W-0 Bit 1 PWM1[1] R/W-0 Bit 0 PWM1[0] R/W-0
A specified value keeps the output of PWM1 to remain at high until such value matches the value of TMR1.
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(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.8 R7 (Port 7 I/O Data, ADC, PWM Duty Cycle)
Page 0 (Port 7 I/O Data Register)
Bit 7 Bit 6 P76 R/W Bit 5 P75 R/W Bit 4 P74 R/W Bit 3 P73 R/W Bit 2 Bit 1 P71 R Bit 0 P70 R/W
Bit 0 (P70): Port 70 is a multi-function pin. In Crystal mode, set P70S in code option to define Port 70 as a general purpose I/O or PLLC. Do not enable the PLL function if Port 70 is defined as an I/O. In IRC or ERIC mode, this pin (Port 70) is defined as general purpose I/O and P70S will be ignored. P70 is Port 70 I/O data register and the IOC7 register can be used to set each bit either as input or output. Bit1 (P71): Port 71 is shared with the /RESET pin. Set the code option for P71S and define Port 71 as an input pin or /RESET pin. This register is a read-only bit. P71 does not does not have an internal pull high function. If you want to use the interrupt at P71, external pull high is necessary. Bit 2 & Bit 7 (undefined): These bits are not used Bit 3 ~ Bit 6 (P73 ~ P76): 4-bit Port 7 I/O data register. The IOC register can be used to set each bit either as input or output. Page 1 (ADC Resolution Selection Bit and ADC MSB Output Data)
Bit 7 Bit 6 Bit 5 AD9 R Bit 4 AD8 R Bit 3 Bit 2 ADRES R/W-0 Bit 1 0 R-0 Bit 0 0 R-0
Bit 0 ~ Bit 1 (undefined): These two bits are not used. However, these bits must be cleared to "0" to avoid possible error. Bit 2 (ADRES): Resolution selection for ADC "0" : ADC is 8-bit resolution. When 8-bit resolution is selected, the most significant (MSB) 8-bit data output of the internal 10-bit ADC will be latched and mapped to RB PAGE1 only (see Section 7.2.12). Hence, R7 PAGE1 Bits 4 ~5 are not implemented. "1" : ADC is 10-bit resolution. When 10-bit resolution is selected, the 10-bit data output of the internal 10-bit ADC will be mapped to RB PAGE1 (see Section 7.2.12), plus R7 PAGE1 Bits 4 ~5 to meet the 10 bits requirement. Bit 3 (undefined): This bit is not used Bit 4 ~ Bit 5 (AD8 ~ AD9): The most significant 2 bits of the 10-bit ADC conversion output data. Combine these two bits with the RB PAGE1 into a complete 10-bit ADC conversion output data. Bit 6 ~ Bit 7 (undefined): These bits are not used
12 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
Page 3 (DT1H: Most Significant Byte (Bit 0 ~ Bit 1) of PWM1 Duty Cycle)
Bit 7 0 R-0 Bit 6 0 R-0 Bit 5 0 R-0 Bit 4 0 R-0 Bit 3 0 R-0 Bit 2 0 R-0 Bit 1 PWM1[9] R/W-0 Bit 0 PWM1[8] R/W-0
Bit 0 ~ Bit 1 (PWM1[8] ~ PWM1[9]): The Most Significant two bits of PWM1 Duty Cycle Bit 2 ~ Bit 7 (undefined): These bits are not used. However, these bits must be cleared to "0" to avoid possible error.
7.2.9 R8 (PWM1 Period)
Page 3 (PRD1: PWM1 Period)
Bit 7 PRD1[7] R/W-0 Bit 6 PRD1[6] R/W-0 Bit 5 PRD1[5] R/W-0 Bit 4 PRD1[4] R/W-0 Bit 3 PRD1[3] R/W-0 Bit 2 PRD1[2] R/W-0 Bit 1 PRD1[1] R/W-0 Bit 0 PRD1[0] R/W-0
The contents of this register is PWM1 time base period. The PWM1 frequency is the inverse of the time base period.
7.2.10 R9 (Port 9 I/O Data, DT2L)
Page 0 (Port 9 I/O Data Register)
Bit 7 P97 R/W Bit 6 P96 R/W Bit 5 P95 R/W Bit 4 P94 R/W Bit 3 P93 R/W Bit 2 P92 R/W Bit 1 P91 R/W Bit 0 P90 R/W
Bit 0 ~ Bit 7 (P90 ~ P97): 8-bit Port 9 (0~7) I/O data register. The IOC register can be used to set each bit either as input or output. Page 3 (DT2L: Least Significant Byte (Bit 0 ~ Bit 7) of PWM2 Duty Cycle)
Bit 7 PWM2[7] R/W-0 Bit 6 PWM2[6] R/W-0 Bit 5 PWM2[5] R/W-0 Bit 4 PWM2[4] R/W-0 Bit 3 PWM2[3] R/W-0 Bit 2 PWM2[2] R/W-0 Bit 1 PWM2[1] R/W-0 Bit 0 PWM2[0] R/W-0
A specified value keeps the PWM2 output to remain high until the it matches with the value of TMR2.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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8-Bit Microcontrollers
7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer, DT2H)
Page 0 (PLL Enable Bit, Main Clock Selection Bits, Watchdog Timer Enable Bit)
Bit 7 0 R/W-0 Bit 6 PLLEN R/W-0 Bit 5 CLK2 R/W-0 Bit 4 CLK1 R/W-0 Bit 3 CLK0 R/W-0 Bit 2 Bit 1 Bit 0 WDTEN R/W-0
Bit 0 (WDTEN): Watchdog control bit "0" : Disable watchdog "1" : Enable watchdog The WDTC instruction can be used to clear the watchdog counter. The watchdog counter is a free-running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e., in Sleep mode). During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during Green mode or Normal mode. Without the presacler, the WDT time-out period is approximately 18 ms. Bit 1 ~ Bit 2 (undefined): These bits are not used Bit 3 ~ Bit 5 (CLK0 ~ CLK2): Main clock selection bits in Crystal mode. These three bits are NOT used in IRC and ERIC mode. In Crystal Mode: Different frequencies for the main clock can be chosen with the CLK0, CLK1 and CLK2 bits. All available clock selections are listed below:
PLLEN 1 1 1 1 1 1 1 1 0 CLK2 0 0 0 0 1 1 1 1 CLK1 0 0 1 1 0 0 1 1 CLK0 0 1 0 1 0 1 0 1 Sub Clock Main Clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 3.582MHz 3.582MHz 3.582MHz 3.582MHz 14.3MHz 14.3MHz 14.3MHz 14.3MHz don't care CPU Clock 3.582MHz (Normal mode 3.582MHz (Normal mode 3.582MHz (Normal mode 3.582MHz (Normal mode 14.3MHz (Normal mode) 14.3MHz (Normal mode) 14.3MHz (Normal mode) 14.3MHz (Normal mode) 32.768kHz (Green mode
don't care don't care don't care 32.768kHz
Bit 6 (PLLEN): PLL's power control bit is the CPU mode control register. This bit is only used under Crystal mode. Under RC mode, this bit will be ignored. "0" : Disable PLL "1" : Enable PLL
14 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
If PPL is enabled, CPU will operate in Normal mode (high frequency). Otherwise, it will run in Green mode (low frequency, 32768 Hz).
3.58MHz, 14.3MHz CLK2 ~ CLK0 PLL circuit 1 switch ENPLL Sub-clock 32.768kHz 0 System clock
Figure 6-2 Correlation between 32.768kHz and PLL
Bit 7 (undefined): This bit is not used. However, always keep this bit at "0" to preclude possible error. When Bit 7and Bit 6 are set to "0" and are included in the SLEP instruction, the following table shows the status after wake up and the wake-up sources.
Wake-up Signal TCC time out IOCF Bit 0 =1 Counter 1 time out IOCF Bit 1=1 WDT time out Port 7 (0, 1, 3)* Sleep Mode RA(7,6)=(0,0) + SLEP No effect No effect Reset and jump to Address 0 Reset and Jump to Address 0
* Port 70
Port 71 Port 73
wake-up function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit 7). wake-up function is controlled by IOCF Bit 4. It is a falling edge trigger. wake-up function is controlled by IOCF Bit 7. It is a falling edge trigger.
Page 3 DT2H: Most Significant Bit (Bit 1 ~ Bit 0) of PWM2 Duty Cycle
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 PWM2[9] R/W-0 Bit 0 PWM2[8] R/W-0
Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): Most Significant bit of PWM2 Duty Cycle A specified value keeps the PWM2 output to remain high until the it matches with the value of TMR2. Bit 2 ~ Bit 7 (undefined): These bits are not used
* 15
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(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.12 RB (ADC Input Data Buffer)
Page 1 (ADC Output Data Register)
Bit 7 AD7 R Bit 6 AD6 R Bit 5 AD5 R Bit 4 AD4 R Bit 3 AD3 R Bit 2 AD2 R Bit 1 AD1 R Bit 0 AD0 R
Bit 0 ~ Bit 7 (AD0 ~ AD7): The last significant 8 bits of the 10-bit or the 8-bit resolution ADC conversion output data. Combine these 8 bits with the R7 PAGE1 Bit 4 ~ Bit 5 (see Section 7.2.8) to have a complete 10-bit ADC conversion output data in 10-bit resolution mode. Page 3 (PRD2: PWM2 Period)
Bit 7 PRD2[7] R/W-0 Bit 6 PRD2[6] R/W-0 Bit 5 PRD2[5] R/W-0 Bit 4 PRD2[4] R/W-0 Bit 3 PRD2[3] R/W-0 Bit 2 PRD2[2] R/W-0 Bit 1 PRD2[1] R/W-0 Bit 0 PRD2[0] R/W-0
Bit 0 ~ Bit 7 (PRD2[0] ~ PRD2[7]): All the contents of this register are PWM2 timebase period. The PWM2 frequency is the inverse of the period.
7.2.13 RC (Port C I/O Data, Counter 1 Data)
Page 0 (Port 9 I/O Data Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PC2 R/W Bit 1 PC1 R/W Bit 0 -
Bit 0 (undefined): This bit is not used. Bit 1 ~ Bit 2 (PC1 ~ PC2): Port C1, Port C2 I/O data register The IOC register can be used to define each bit either as input or output. Bit 3 ~ Bit 7 (undefined): These bits are not used. Page 1 (Counter 1 Data Register)
Bit 7 CN17 R/W-0 Bit 6 CN16 R/W-0 Bit 5 CN15 R/W-0 Bit 4 CN14 R/W-0 Bit 3 CN13 R/W-0 Bit 2 CN12 R/W-0 Bit 1 CN11 R/W-0 Bit 0 CN10 R/W-0
Bit 0 ~ Bit 7 (CN10 ~ CN17): Counter 1 buffer that's readable and writable. Counter 1 is an 8-bit up-counter with 8-bit prescaler that allows the device to preset (write preset) and read the counter by using RC PAGE1. After an interrupt, the preset value will be reloaded. Examples of Write & Read Instructions: MOV MOV 0x0C, A A, 0x0C ; write the data at accumulator to Counter 1 (preset) ; read & move the data at Counter 1 to accumulator
16 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.14 RE (Interrupt Flag)
Page 0 (Interrupt Flag)
Bit 7 PWM2 R/W-0 Bit 6 0 R/W-0 Bit 5 ADI R/W-0 Bit 4 PWM1 R/W-0 Bit 3 0 R/W-0 Bit 2 0 R/W-0 Bit 1 0 R/W-0 Bit 0 0 R/W-0
Bit 0 ~ Bit 3 (undefined): Not used. However, these four bits must be cleared to "0" to prevent possible error. Bit 4 (PWM1): One PWM1 (Pulse Width Modulation Channel 1) period upon reaching interrupt flag. Bit 5 (ADI): ADC interrupt flag after each sampling
Bit 6 (undefined): This bit must be cleared to "0." Otherwise, errors may occur. Bit 7 (PWM2): PWM2 (Pulse Width Modulation Channel 2) interrupt flag Set when a selected period is reached, reset by software.
7.2.15 RF (Interrupt Status)
Interrupt Status Register
Bit 7 INT3 R/W-0 Bit 6 Bit 5 Bit 4 INT1 R/W-0 Bit 3 INT0 R/W-0 Bit 2 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows. "0" : With Interrupt request "1" : No Interrupt request. Hence no interrupt occurs. Bit 1 (CNT1): Counter1 timer overflow interrupt flag. Set when Counter1 timer overflows. "0" : With Interrupt request "1" : No Interrupt request. Hence no interrupt occurs. Bit 2 (undefined): This bit is not used Bit 3 (INT0): By setting Port 70 to general IO, INT0 will become Port 70 pin's interrupt flag. If Port 70 has a falling edge/rising edge (controlled by the CONT register) trigger signal, the CPU will set this bit. If the pin is set to PLLC or OSCI, no interrupt will occur at Port 70 and INT0 register will be ignored. "0" : With Interrupt request "1" : No Interrupt request. Hence no interrupt occurs.
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(This specification is subject to change without further notice)
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8-Bit Microcontrollers
Bit 4 (INT1): By setting Port 71 to general IO, INT1 will become Port 71 pin's interrupt flag. External pull high circuit is needed to trigger an interrupt at Port 71. If Port 71 has a falling edge trigger signal, the CPU will set this bit. If the pin is set to /RESET, no interrupt will occur at Port 71 and INT1 register will be ignored. "0" : With Interrupt request "1" : No Interrupt request. Hence no interrupt occurs. Bit 5 ~ Bit 6 (undefined): These bits are not used Bit 7 (INT3): External Port 73 pin interrupt flag. If Port 73 has a falling edge trigger signal (see table below), the CPU will set this bit. "0" : With Interrupt request "1" : No Interrupt request. Hence no interrupt occurs.
NOTE IOCF is the interrupt mask register which can be read from and cleared.
The following shows the trigger edge signals.
Signal TCC Counter 1 INT0 INT1 INT3 Trigger Time out Time out Falling / Rising edge Falling edge Falling edge
7.2.16 R10~R3F (General Purpose Register)
R10~ R3F (Banks 0 ~ 3) These are all general purpose registers.
7.3
Special Function Registers
7.3.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register.
7.3.2 CONT (Control Register)
Bit 7 P70EG R/W-1 Bit 6 INT R/W-0 Bit 5 TS R/W-1 Bit 4 RETBK R/W-1 Bit 3 PAB R/W-1 Bit 2 PSR2 R/W-1 Bit 1 PSR1 R/W-1 Bit 0 PSR0 R/W-1
Note: The CONT register is readable (CONTR) and writable (CONTW).
18 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
Bit 0 ~ Bit 2 (PSR0 ~ PSR2): TCC/WDT prescaler bits
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Ratio 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 3 (PAB): Prescaler assigned bit "0" : TCC "1" : WDT Bit 4 (RETBK): Return the backed-up control value for the interrupt routine "0" : Disable "1" : Enable When this bit is set to "1", the CPU will store ACC, R3 status, and R5 PAGE automatically after an interrupt is triggered. This bit will be restored after the RETI instruction. When this bit is set to "0", user needs to store ACC, R3 status, and R5 PAGE in the program. Bit 5 (TS): TCC signal source "0" : Internal instruction clock cycle "1" : IRC output Bit 6 (INT): INT enable flag "0" : Interrupt masked by DISI or hardware interrupt "1" : Interrupt enabled by ENI/RETI instructions Bit 7 (P70EG): If Port 70 is set to INT0 input, P70EG can select the interrupt toggle type. "0" : P70 's interrupt source is a rising edge signal and falling edge signal "1" : P70 's interrupt source is a falling edge signal TCC and WDT An 8-bit counter is available as the prescaler for the TCC or WDT. The prescaler is available for either TCC or WDT at a time. Availability of the 8-bit counter for TCC or WDT is contingent on the status of Bit 3 (PAB) of the CONT register as shown above. See the prescaler ratio for TCC/WDT in the table above. Figure 6-3 below depicts the block diagram of TCC/WDT.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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8-Bit Microcontrollers
OSCM1,0
PLL Output IRC oscillator ERIC oscillator OSCM1,0
Xtal 32.768k IRC oscillator ERIC oscillator
/2
Figure 7-3 TCC/WDT Block Diagram
7.3.3 IOC6 (Port 6 I/O Control, P6 Pin Switch Control)
Page 0 (Port 6 I/O Control Register)
Bit 7 0 Bit 6 0 Bit 5 IOC65 R/W-1 Bit 4 IOC64 R/W-1 Bit 3 IOC63 R/W-1 Bit 2 IOC62 R/W-1 Bit 1 IOC61 R/W-1 Bit 0 IOC60 R/W-1
Bit 0 ~ Bit 1 (IOC60 ~ IOC61): In IRC or ERIC mode, Port 60 and Port 61 are I/O direction control registers. In Crystal mode, these two bits are unused. Bit 2 ~ Bit 5 (IOC62 ~ IOC65): Port 62 ~ Port 65 I/O direction control register "0" : Set the corresponding I/O pin as output "1" : Set the corresponding I/O pin to high impedance Bit 6 ~ Bit 7 (undefined): These bits are not used. However, these two bits must be cleared to "0." Otherwise, the MCU power consumption will increase.
NOTE The default value of these bits is "1." Clear them to "0" when initializing the MCU.
20 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers Page 1 (Port 6 Pins Switch Control Register)
Bit 7 Bit 6 0 Bit 5 P65S R/W-0 Bit 4 P64S R/W-0 Bit 3 P63S R/W-0 Bit 2 P62S R/W-0 Bit 1 P91S R/W-0 Bit 0 P90S R/W-0
Bit 0 (P90S): Select normal I/O Port90 pin or ADC Channel 1 input AD1 pin "0" : P90 (I/O Port 90) pin is selected "1" : AD1 (ADC Channel 1 input) pin is selected Bit 1 (P91S): Select normal I/O Port 91 pin or Channel 2 input AD2 pin of ADC "0" : P91 (I/O Port 91) pin is selected "1" : AD2 (ADC Channel 2 input) pin is selected Bit 2 (P62S): Select normal I/O Port 62 pin or Channel 3 input AD3 pin of ADC "0" : P62 (I/O Port 62) pin is selected "1" : AD3 (ADC Channel 3 input) pin is selected Bit 3 (P63S): Select normal I/O Port 63 pin or Channel 4 input AD4 pin of ADC "0" : P63 (I/O Port 63) pin is selected "1" : AD4 (ADC Channel 4 input) pin is selected Bit 4 (P64S): Select normal I/O Port 64 pin or Channel 5 input AD5 pin of ADC "0" : P64 (I/O Port 64) pin is selected "1" : AD5 (ADC Channel 5 input) pin is selected Bit 5 (P65S): Select normal I/O Port 65 pin or Channel 6 input AD6 pin of ADC "0" : P65 (I/O Port 65) pin is selected "1" : AD5 (ADC Channel 6 input) pin is selected Bit 6 (undefined): This bit is not used. However, it must be cleared to "0" to prevent possible error from occuring. Bit 7 (undefined): This bit is not used
NOTE 1. ADC Channel 1 and Channel 2 are shared with Port 90 and Port 91. 2. ADC Channel 3 and Channel 6 are shared with Port 62 and Port 65.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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8-Bit Microcontrollers
7.3.4 IOC7 (Port 7 I/O Control, Port 7 Pull-high Control)
Page 0 (Port 7 I/O Control Register)
Bit 7 0 Bit 6 IOC76 R/W-1 Bit 5 IOC75 R/W-1 Bit 4 IOC74 R/W-1 Bit 3 IOC73 R/W-1 Bit 2 0 Bit 1 0 Bit 0 IOC70 R/W-1
Bit 0 (IOC70): Port 70 pin is defined as general purpose IO, PLLC, or OSC through code option setting. In IRC mode or Crystal mode (only at code option P70S =0 ), Port 70 pin is a general purpose IO, while IOC70 is I/O direction control register of Port 70 pin. "0" : Set the corresponding I/O pin as output "1" : Set the corresponding I/O pin to high impedance Bit 1 (undefined): This bit is not used. However, by setting P71S = 1 through code option, Port 71 pin will become an input-only pin. Bit 2 (undefined): This bit is not used but must be cleared to "0." Otherwise, the MCU power consumption will increase.
NOTE The default value of this bit is "1." Clear to "0" when initializing the MCU.
Bit 3 ~ Bit6 (IOC73~IOC76): Port 7 I/O direction control register "0" : Set the corresponding I/O pin as output "1" : Set the corresponding I/O pin to high impedance Bit 7 (undefined): This bit is not used but must be cleared to "0." Otherwise, the MCU power consumption will increase.
NOTE The default value of this bit is "1." Clear to "0" when initializing the MCU.
Page 1 (Port 7 Pull-high Control Register)
Bit 7 0 Bit 6 PH76 R/W-0 Bit 5 PH75 R/W-0 Bit 4 PH74 R/W-0 Bit 3 PH73 R/W-0 Bit 2 0 Bit 1 0 Bit 0 PH70 R/W-0
Bit 0 (PH70): Port 70 pull high control register. This bit only exists whe you set Port 70 as a general purpose IO. "0" : disable pull high function "1" : enable pull high function Bits 1 ~ 2 & Bit 7 (undefined): These bits are not used but must be cleared to "0." Otherwise, the MCU power consumption will increase. Bit 3 ~ Bit 6 (PH73 ~ PH76): Port 7 pull high control register "0" : disable pull high function "1" : enable pull high function
22 * Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.3.5 IOC9 (Port 9 I/O Control, Port 9 Switches)
Page 0 (Port 9 I/O Control Register)
Bit 7 IOC97 R/W-1 Bit 6 IOC96 R/W-1 Bit 5 IOC95 R/W-1 Bit 4 IOC94 R/W-1 Bit 3 IOC93 R/W-1 Bit 2 IOC92 R/W-1 Bit 1 IOC91 R/W-1 Bit 0 IOC90 R/W-1
Bit 0 ~ Bit 7 (IOC90 ~ IOC97): Port 9 (0~7) I/O direction control register "0" : Set the corresponding I/O pin as output "1" : Set the corresponding I/O pin to high impedance
7.3.6 IOCA (Port 9 PMS Switch Control)
Page 1 (Port 9 Pin Switch Control Register)
Bit 7 Bit 6 0 R/W Bit 5 Bit 4 Bit 3 0 R/W Bit 2 Bit 1 AD8S R/W-0 Bit 0 AD7S R/W-0
Bit 0 (AD7S): Select normal I/O Port 92 pin or ADC Channel 7 input AD7 pin "0" : P92 (I/O Port 92) pin is selected "1" : AD7 (ADC Channel 7 input ) pin is selected Bit 1 (AD8S) : Select normal I/O Port 93 pin or ADC Channel 8 input AD8 pin "0" : P93 (I/O Port 93) pin is selected "1" : AD8 (ADC Channel 8 input ) pin is selected Bit 2 (undefined): This bit is not used Bit 3 (undefined): This bit is not used. However, it must be cleared to "0." Otherwise, the MCU power consumption will increase. Bit 4 ~ Bit 5 (undefined): These bits are not used. Bit 6 (undefined): This bit is not used. However, this bit must be cleared to "0." Otherwise, the MCU power consumption will increase. Bit 7 (undefined): This bit is not used.
7.3.7 IOCB (ADC Control)
Page 1 (ADC Control Bits)
Bit 7 IN2 R/W-0 Bit 6 IN1 R/W-0 Bit 5 IN0 R/W-0 Bit 4 ADCLK1 R/W-0 Bit 3 ADCLK0 R/W-0 Bit 2 ADPWR R/W-0 Bit 1 0 Bit 0 ADST R/W-0
Bit 0 (ADST): Start sampling at the AD converter By setting this bit to "1", the AD will start to sample data. This bit will be cleared by hardware automatically after each sampling.
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(This specification is subject to change without further notice)
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8-Bit Microcontrollers
Bit 1 (undefined): This bit is not used. However, it must be cleared to "0" to preclude possible error. Bit 2 (ADPWR): AD converter power control "0" : disable "1" : enable Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1): AD circuit`s sampling clock source. In Crystal mode:
ADCLK1 0 0 1 1 ADCLK0 0 1 0 1 Sampling Rate 74.6K 37.4K 18.7K 9.3K Operating Voltage >=3.5V >=3.0V >=2.5V >=2.5V
In IRC or ERIC mode: In these modes, the AD converter rate is set by the oscillator. The formula for the input frequency and the AD converter rate is:
AD Converter rate =
Oscillator / 4 2 ADCLK / 12
(
)
For example, if input CLK = 4MHz:
ADCLK1 0 0 1 1 ADCLK0 0 1 0 1 Sampling Rate 83.3K 41.7K 20.8K 10.4K Operation Voltage >=3.5V >=3.0V >=2.5V >=2.5V
Note: The AD converter (ADC) rate must not be over 50kHz. Otherwise, the ADC resolution will decrease.
This is a CMOS multi-channel 10-bit successive approximation of the A/D converter. Its features are as follows:
* 74.6kHz maximum conversion speed (Crystal mode) at 5V * Adjustable full scale input * Internal (VDD) reference voltage * Eight analog inputs multiplexed into one AD converter * Power-down mode for power saving * Complete AD conversion interrupt * Interrupt register, AD control, and status register, and AD data register
24 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
PLL
fpll
Programmable divider 1/Mx
fs
Divider Nx
fadc
10-bit ADC
ADC output
ADCLK1~ADCLK0
ENPLL
CLK2 ~ CLK0
Figure 7-4 ADC Voltage Control Logic
Bit 5 ~ Bit 7 (IN0~ IN2) : Input channel selection of the AD converter. These two bits can choose one of the following three AD inputs.
IN2 0 0 0 0 1 1 1 1 IN1 0 0 1 1 0 0 1 1 IN0 0 1 0 1 0 1 0 1 Input AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 Pin P90 P91 P62 P63 P64 P65 P92 P93
NOTE Before switching to the AD channel, the corresponding pin must be set as an AD input.
7.3.8
Bit 7 0 -
IOCC (Port C I/O Control, ADC Control)
Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 IOCC2 R/W-1 Bit 1 IOCC1 R/W-1 Bit 0 0 -
Page 0 (Port C I/O Control)
Bit 0 (undefined): This bit is not used. However, it must be cleared to "0." Otherwise, the MCU power consumption will increase. Bit 1 ~ Bit 2 (IOCC1 ~ IOCC2): PORTC (1~2) I/O direction control register "0" : Set the corresponding I/O pin as output "1" : Set the corresponding I/O pin to high impedance Bit 3 ~ Bit 7 (undefined): This bit is not used. However, it must be cleared to "0." Otherwise, the MCU power consumption will increase.
NOTE The default value of Bit 0 and Bits 3~7 is "1." Clear to "0" when initializing the MCU
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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7.3.9
IOCD (Tone 1 Control, Clock Source, CN1 Prescaler)
Page 1 (Clock Source and Counter 1 Prescaler)
Bit 7 CNTI/ES R/W-0 Bit 6 Bit 5 Bit 4 Bit 3 CNT1S R/W-0 Bit 2 Bit 1 Bit 0
C1_PSC2 C1_PSC1 C1_PSC0 R/W-0 R/W-0 R/W-0
Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2): Counter 1 prescaler ratio
C1_PSC2 0 0 0 0 1 1 1 1 C1_PSC1 0 0 1 1 0 0 1 1 C1_PSC0 0 1 0 1 0 1 0 1 Counter 1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (CNT1S): Counter 1 clock source. This bit will be unchanged under RC mode (RC mode CLK is always equal to the oscillator's frequency). "0" : 16.384kHz "1" : System clock
Figure 6-5 Timer CLK Source Diagram
Bit 4 ~ Bit 6 (undefined): These bits are not used Bit 7 (CNTI/ES): Counter source select "0" : Timer counter CLK is sourced from the system CLK or Crystal output, and P94 is set as a general purpose I/O "1" : P94 is defined as input, and the Timer counter CLK is sourced from P94's falling edge
26 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.3.10 IOCE (Interrupt Mask)
Page 0 (Interrupt Mask)
Bit 7 PWM2 R/W-0 Bit 6 0 Bit 5 ADI R/W-0 Bit 4 PWM1 R/W-0 Bit 3 Bit 2 Bit 1 Bit 0 -
Bit 1 ~ Bit 3 (undefined): These bits are not used. Bit 4 (PWM1) : One PWM1 one period for each interrupt mask. Bit 5 (ADI) : ADC conversion complete interrupt mask "0" : Disable interrupt "1" : Enable interrupt There are four registers for the AD converter. Use one bit of the interrupt control register (IOCE Page 0 Bit 5) to signal an interrupt when the AD conversion is completed. The status and control register of AD (IOCB Page 1 and RE Page 0 Bit 5) indicate the A/D conversion status or AD control. The AD data register (RB PAGE1) stores the result of the AD conversion. The ADI bit can be enabled or disabled in the IOCE PAGE 0 register to signal the completion of the A/D conversion. The ADI flag is then enabled or disabled in the RE register when AD conversion is completed. The ADI flag indicates the end of an AD conversion. The AD converter sets the interrupt flag (ADI) in the RE Page 0 register when a conversion is completed. The interrupt can be disabled by setting the ADI bit in IOCE Page 0 Bit 5 to "0." The AD converter has eight analog input channels (AD1 ~ AD8) multiplexed into one sample and hold to AD module. The reference voltage can be driven from the internal power. The AD converter itself is a 10-bit successive approximation type and produces the last significant 8-bit result in the RB Page 1 and the most significant 2 bits to R7 Page 1 Bit 4, Bit 5. A conversion is initiated by setting a control bit ADST in IOCB Page 1 Bit 0. Prior to conversion, the appropriate channel must be selected by setting IN0 ~ IN2 bits in the RE register. Enough time must be allowed to sample data. Every AD data conversion needs 12-clock cycle time. The minimum conversion time required is 13 s (73K sample rate). The ADST Bit in IOCB Page 1 Bit 0 must be set to begin a conversion. It will be automatically reset in the hardware when a conversion is completed. At the end of the conversion, the Start bit is cleared and the the AD interrupt is activated if ADI in IOCE Page 0 Bit 5 = 1. ADI will be set when the conversion is completed. It can be reset in the software. If ADI = 0 in IOCE Page 0 Bit 5 and AD starts data conversion by setting ADST(IOCB Page 1 Bit 0) = 1, then AD will continue the conversion non-stop and the hardware
* 27
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers won't reset the ADST bit. In this condition, ADI is deactived. After ADI in IOCE Page 0 Bit 5 is set, ADI in RE Page 0 Bit 5 will beactivated again. To minimize the operating current, all biasing circuits in the A/D module that consume DC current, are powered down when the ADPWR bit in IOCB Page 1 Bit 2 register is "0." When ADPWR bit is "1," the A/D converter module is operating.
1 2 3 4 5 6 7 8 9 10
Start
Sample ADI (IOCE Page 0 Bit 5 ) =1 ADI (RE Page 0 Bit 5) Data Cleared by software
Figure 7-6 A/D Converter Timing
Bit 6 (undefined): This bit is not used. However, you must clear this bit to "0" to avoid possible error. Bit 7 (PWM2) : PWM2 interrupt enable bit "0" : Disable interrupt "1" : Enable interrupt
7.3.11 IOCF (Interrupt Mask)
Page 0 (Interrupt Mask Register)
Bit 7 INT3 R/W-0 Bit 6 0 Bit 5 0 Bit 4 INT1 R/W-0 Bit 3 INT0 R/W-0 Bit 2 0 Bit 1 CNT1 R/W-0 Bit 0 TCIF R/W-0
Bit 0 ~ Bit 1 (TCIF ~ CNT1): Interrupt enable bits "0" : Disable interrupt "1" : Enable interrupt Bit 2 (undefined): This bit is not used. However, this bit must be cleared to "0" to avoid unpredicted interrupts to occur. Bits 3 ~ Bit 4 (INT0 ~ INT1): Interrupt enable bits "0" : Disable interrupt "1" : Enable interrupt Bit 5 ~ Bit 6 (undefined): These bits are not used. However, these bits must be cleared to "0" to avoid unpredicted interrupts to occur. Bits 7 (INT3): Interrupt enable bit "0" : Disable interrupt "1" : Enable interrupt
28 * Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
The following table shows the interrupt sources and the resulting status after an interrupt.
Interrupt Signal TCC time out IOCF Bit 0=1 And "ENI" DISI No function No function No function ENI Sleep Mode RESET and Jump to Address 0 Green Mode Interrupt (Jump to Address 8 at Page 0) Normal Mode Interrupt (Jump to Address 8 at Page 0)
Counter 1 time out IOCF Bit 1=1 And "ENI" Port 701 Only at IRC mode or Crystal mode (at P70S = 0) Port 712 Only at P71S = 0 Port 733 IOCF Bit3 Bit 7 =1 And "ENI" ADI4 IOCE Bit5 = 1 And "ENI PWM1 IOCE Bit4 = 1 And "ENI
1 Port 2
No function
Interrupt (Jump to Address 8 at Page 0)
Interrupt (Jump to Address 8 at Page 0)
RESET and Jump to Address 0
Interrupt (Jump to Address 8 at Page 0) Interrupt (Jump to Address 8 at Page 0) Interrupt (Jump to Address 8 at Page 0)
Interrupt (Jump to Address 8 at Page 0) Interrupt (Jump to Address 8 at Page 0) Interrupt (jump to Address 8 at Page0) Interrupt
RESET and Jump to Address 0
RESET and Jump to Address 0
No function
No function
(Jump to Address 8 at Page 0) Interrupt (Jump to Address 8 at Page 0)
Interrupt No function (Jump to Address 8 at Page 0)
70 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger (controlled by CONT register Bit 7). Port 71 interrupt function is controlled by IOCF Bit 4. It is a falling edge trigger. 73 interrupt function is controlled by IOCF Bit 7. It is a falling edge trigger. interrupt source function is controlled by RE Page 0 Bit 5. It is a rising edge trigger after an ADC sampling is completed.
3 Port 4 ADI
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.4
Instruction Set
The Instruction set has the following features: 1) Every bit of any register can be set, cleared, or tested directly. 2) The I/O register can be regarded as general register. That is, the same instruction can operate on the I/O register.
Convention: R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in register R and which affects the operation. k = 8 or 10-bit constant or literal value
Binary Instruction
0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr
Hex
0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr
Mnemonic
NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R
Operation
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 Bits 9,10, do not clear AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA
Status Affected
None C None T, P T, P None None None None None None None Z, C, DC None Z Z Z, C, DC Z, C, DC Z Z Z Z Z Z Z Z Z,C, DC Z,C, DC Z
Instruction Cycle
1 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1
30 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
Binary Instruction
0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr
Hex
04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr
Mnemonic
MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RR /R A /R R R+1 A R+1 R
Operation
Status Affected
Z Z Z Z Z None None C
Instruction Cycle
1 1 1 1 1 2 if skipped 2 if skipped 1
1 1
R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A
0 0110 01rr rrrr
06rr
RRC R
C
1
0 0110 10rr rrrr
06rr
RLCA R
C
1
0 0110 11rr rrrr
06rr
RLC R
C
1
0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1110 100k kkkk 1 1111 kkkk kkkk
1
07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk
SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
None None None None None None None None None None None Z Z Z None Z, C, DC None None Z, C, DC
1 1 2 if skipped 2 if skipped 1 1 2 if skipped 2 if skipped 2 2 1 1 1 1 2 1 1 1 1
1
One Instruction cycle = Two main CLK
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 31
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.5
Bit 12 IR3 IR2
Code Option Register
Bit 10 IR1 Bit 9 IR0 Bit 8 P71S Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 /POT0 P70S OSCM1 OSCM0 IRC2S
Bit 11
Bit 0 (/POT0): Program ROM protect option If this bit is set to "1," you can access the program memory; else if this bit is "0," you cannot access the program memory. Bits 1~2: Bit 3: Not used (reserved). These bits are always set to "1" Not used (reserved). This bit is always set to "0"
Bit 4 (IRC2S): Select internal RC oscillation frequency (for system CLK) "0" : 2MHz "1" : 4MHz Bit 5 ~ Bit 6 (OSCM0 ~ OSCM1): Select Oscillation mode
OSCM1 0 0 1 OSCM0 0 1 x Oscillation Mode IRC mode ERIC mode Crystal mode
Bit 7 (P70S): Port 70 function select bit
OSCM1 0 0 1 1 OSCM0 0 1 x x P70S x x 1 0 Port 70 Status General Purpose IO OSC input, you must cascade resister to AVDD PLLC output, you must cascade capacitor to AVSS General Purpose IO, PLL function will be disabled
Bit 8 (P71S): Port 71 function select bit "0" : /RESET pin is selected "1" : General purpose input port Port 71 is selected Bit 9 ~ Bit 12 (IR0 ~ IR3): Internal RC mode Calibrator IR0~3 must be set to "1" only (IRC frequency auto calibration).
32 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.6
I/O Port
7.6.1 I/O Structure
The I/O registers are bidirectional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O data registers and I/O control registers are both readable and writable. The I/O ports and control registers circuits are illustrated below.
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Figure 7-7a I/O Port and I/O Control Register Circuit
Figure 7-7b EM785840N/41N/42N Input/output Ports Circuit
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.6.2
I/O Description
Pin P65 R65, Page 0 I/O IOC65, Page 0 AD6 P64 R64, Page 0 I/O IOC64, Page 0 AD5 P63 R63, Page 0 I/O IOC63, Page 0 AD3 P62 R62, Page 0 I/O IOC62, Page 0 AD3 P61 R61, Page 0 I/O IOC61, Page 0 Xin P60 R60, Page 0 I/O IOC60, Page 0 Xout
Port 6
Register I/O I/O Control Pin-shared with
Port 60 ~ Port 61: Used in IRC and ERIC mode In these two modes, Port 60 and Port 61 are defined as general purpose IO. In Crystal mode, Port 60 and Port 61 are defined as crystal input (Xin and Xout) pins and R60, R61 bits are undefined. Port 62 ~ Port 65: Port 6 (2~5) I/O pins The IOC register can be used to define each pin as input or output. IOC60 ~ IOC61: Unused registers in Crystal mode In IRC or ERIC mode, these bits are I/O direction control register. Port 7
Pin Register I/O I/O control Pull high Pin-shared with P76 P75 P74 P73 R73, Page0 I/O IOC73, Page 0 IOC73, Page 1 INT3 P71 P70
R76, Page R75, Page R74, Page 0 0 0 I/O IOC76, Page 0 IOC76, Page 1 I/O IOC75, Page 0 IOC75, Page 1 I/O IOC74, Page 0 IOC74, Page 1 -
R71, Page R70, Page 0 0 Input only x x Reset/INT0 I/O IOC70, Page 0 IOC70, Page 1 PLLC/ERIC /INT0
Port 70: Multifunction pin In Crystal mode, by setting P70S in code option, Port 70 will be set as general purpose I/O or PLLC.
NOTE Do not enable the PLL function if Port 70 is defined as I/O.
34 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
In IRC or ERIC mode, this pin is defined as Port 70, and P70S will be ignored. R70, Page 0 is a Port 70 I/O data register. The IOC register can be used to define each bit either as input or output. Port 71: is shared with /RESET pin. By setting P71S in code option, Port 71 is defined to Input pin or /RESET pin. This is an input only pin. P71 does not support internal pull-high function. If you want to use P71 interrupt, external pull high is necessary. Port 73 ~ Port 76: Port 7 I/O pins The IOC register can be used to define each bit either as input or output. IOC70, Page 1: is Port 70 pull high control register. This bit only exist when Port 70 is set as general purpose IO. Port 9
Pin P97 P96 P95 P94 P93 P92 P91 P90
Register R97, Page 0 R96, Page 0 R95, Page 0 R94, Page 0 R93, Page 0 R92, Page 0 R91, Page 0 R90, Page 0 I/O I/O Control Shared with I/O IOC96, Page 0 I/O IOC96, Page 0 I/O IOC95, Page 0 I/O IOC94, Page 0 CIN I/O IOC93, Page 0 AD1 I/O IOC92, Page 0 AD1 I/O IOC91, Page 0 AD1 I/O IOC90, Page 0 AD1
P90 ~ P97: Port 9 I/O pins The IOC register can be used to define each bit either as input or output. Port C
Pin Register PC2 RC1, Page0 I/O I/O control Shared with PC1 RC1, Page0 I/O
IOCC2, Page0 IOCC1, Page0 PWM2 PWM1
PC1~PC2: Port C I/O pins The IOC register can be used to define each bit either as input or output.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 35
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.7
Reset
A Reset is initiated by one of the following conditions: Power-on reset WDT timeout (if enabled and in Green or Normal mode) The Reset pin is pulled low (At P71S = 1) Once a Reset occurs, the following functions are immediatley performed: The oscillator continues to run, or will be started (if not already running) The Program Counter (R2) is set to all "0" When powered on, the upper three bits of R3 and the upper two bits of R4 are cleared. The Watchdog timer and prescaler counter are cleared. The Watchdog timer is disabled.
7.8
Wake-Up
The controller provides a Sleep mode function to conserve power consumption bySleep mode, RA(7) = 0 + "SLEP" instruction In Sleep mode, the controller turns off all the CPU and crystal. Other power control circuits can also be turned off, i.e., key tone control or PLL control (which has an enable register) by software. Wake-up is triggered from Sleep mode through one of the following conditions: WDT Time-out External interrupt /RESET pull low All of the above will reset the controller and run the program at Address 0. The result is the same as that with power-on reset.
36 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
The following table lists the wake-up sources and the resulting status after wake-up:
Wake-up Signal TCC Time-out IOCF Bit 0=1 Counter 1 Time out IOCF Bit 1=1 WDT Time out Port 7 (0, 1, 3)* Sleep Mode RA (7, 6)=(0, 0) + SLEP No function No function Reset and Jump to Address 0 Reset and Jump to Address 0
* Port 70 wake-up function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger
(controlled by CONT register Bit7). Port 71 wake-up function is controlled by IOCF Bit 4. It is a falling edge trigger. Port 73 wake-up function is controlled by IOCF bit 7. It is a falling edge trigger.
7.9
Interrupt
RF is the interrupt status register that records the interrupt request in a flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) is generated, it will prompt the next instruction to be fetched from Address 008H. Once in the interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared through software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
7.10 PWM (Pulse Width Modulation)
7.10.1 Overview
In PWM mode, both PWM1 and PWM2 pins produce up to 10-bit resolution PWM output (see Figure 7-8a below for its functional block diagram). A PWM output has a period and a duty cycle, and it keeps the output in high. The baud rate of the PWM is the inverse of the period. Figure 6-8b below illustrates the relationships between a period and a duty cycle.
DL2H + DL2L
latch To PWM1IF
Fosc 1:2 1:8 1:32 1:64
DT2H + DT2L Comparator MUX
TMR1H + TMR1L
reset
Duty Cycle Match
PWM1 R S
IOC6
Q
Comparator
T1P0 T1P1 T1EN
Period Match
PRD1 Data Bus
DL2H + DL2L
latch
Data Bus
To PWM2IF
T2P0 T2P1 T2EN
DT2H + DT2L
Comparator
Duty Cycle Match
PWM2 Fosc 1:2 1:8 1:32 1:64
TMR2H + TMR2L
reset
R S
Q
MUX Comparator
IOC6 Period Match
PRD2
Figure 7-8a Dual PWM Functional Block Diagram
Period
Duty Cycle DT1 = TMR1
PRD1 = TMR1
Figure 7-8b PWM Output Timing
38 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.10.2 Relative Register Description
R5, Page 3 (PWMCON)
Bit 7 PWM2E Bit 6 PWM1E Bit 5 T2EN Bit 4 T1EN Bit 3 T2P1 Bit 2 T2P0 Bit 1 T1P1 Bit 0 T1P0
Bit 0 ~ Bit 1 (T1P0 ~ T1P1): TMR1 clock prescaler option bits
T1P1 0 0 1 1 T1P0 0 1 0 1 Prescaler 1:2 (Default) 1:8 1:32 1:64
Bit 2 ~ Bit 3 (T2P0 ~ T2P1): TMR2 clock prescaler option bits
T1P1 0 0 1 1 T1P0 0 1 0 1 Prescaler 1:2 (Default) 1:8 1:32 1:64
Bit 4 (T1EN): TMR1 enable bit "0" : TMR1 is off (default value) "1" : TMR1 is on Bit 5 (T2EN): TMR2 enable bit "0" : TMR2 is off (default value) "1" : TMR2 is on Bit 6 (PWM1E): PWM1 enable bit "0" : WM1 is off (default value), and its related pin carries out the PC1 function "1" : PWM1 is on, and its related pin is automatically set as output Bit 7 (PWM2E): PWM2 enable bit "0" : PWM2 is off (default value), and its related pin carries out the PC2 function "1" : PWM2 is on, and its related pin is automatically set as output R6 and R7, Page 3 (DT1: Duty Cycle of PWM1)
R71 R70 R67 R66 R65 R64 R63 R62 R61 R60
PWM1[9] PWM1[8] PWM1[7] PWM1[6] PWM1[5] PWM1[4] PWM1[3] PWM1[2] PWM1[1] PWM1[0]
A specified value keeps the PWM1 output to remain high until the value matches with TMR1.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
R9 and RA, Page 3 (DT2: PWM2 Duty Cycle)
RA1 RA0 R97 R96 R95 R94 R93 R92 R91 R90
PWM2[9] PWM2[8] PWM2[7] PWM2[6] PWM2[5] PWM2[4] PWM2[3] PWM2[2] PWM2[1] PWM2[0]
A specified value keeps the PWM2 output to remain high until the value matches with TMR2. R8, Page 3 (PRD1: PWM1 Period)
Bit 7 PRD1[7] Bit 6 PRD1[6] Bit 5 PRD1[5] Bit 4 PRD1[4] Bit 3 PRD1[3] Bit 2 PRD1[2] Bit 1 PRD1[1] Bit 0 PRD1[0]
This register contains the PWM1 time-base period. The PWM1 frequency is the inverse of the time-base period. RB, Page 3 (PRD2: PWM2 Period)
Bit 7 PRD2[7] Bit 6 PRD2[6] Bit 5 PRD2[5] Bit 4 PRD2[4] Bit 3 PRD2[3] Bit 2 PRD2[2] Bit 1 PRD2[1] Bit 0 PRD2[0]
This register contains the PWM2 time-base period. The PWM2 frequency is the inverse of the time-base period.
7.10.3 Increment Timer Counter (TMRX: TMR1H/TMR1L or TMR2H/TMR2L)
TMRX are 10-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions. If enabled, the rates can be reduced to conserve power by setting the T1EN bit to "0".
7.10.4 PWM Period (PRDX: PRD1 or PRD2)
The PWM period is defined by writing to the PRDX register. When TMRX is equal to PRDX, the following operations are performed on the next increment cycle:
* TMRX is cleared * The PWMX pin is set to "1" * The PWM duty cycle is latched from DT1/DT2 to DTL1/DTL2
NOTE The PWM output will not be set if the duty cycle is 0.
* The PWMXIF pin is set to 1
40 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
The following formula is used to calculate the PWM period: Period = (PRDX + 1) x 4 x
1 FOSC
x (TMRX x Prescale value)
Where Fosc is the system clock
7.10.5 PWM Duty Cycle (DTX: DT1H/ DT1L; DTL: DL1H/DL1L)
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded any time. However, it cannot be latched into DTL until the current value of DLX is equal to TMRX. The following formula is used to calculate the PWM duty cycle: Duty Cycle = (DTX ) x
1 FOSC
x (TMRX x Prescale value)
7.10.6 PWM Programming Procedure/Steps
Follow these steps in loading PRDX with the PWM period: 1) Load DTX with the PWM duty cycle 2) Enable interrupt function by writing to IOCF PAFE0, if required 3) Set the PWMX pin as output by writing a desired value to IOCC Page 0 Load a desired value to R5 Page 3 with the TMRX prescaler value and enable both PWMX and TMRX.
7.10.7 Timer (TMRX)
The TMRX, consisting of Timer 1 (TMR1) and Timer 2 (TMR2), are 10-bit clock counters with programmable prescalers. This is designed for the PWM module to be set as baud rate clock generators. TMRX can be read, written, and cleared at any reset conditions.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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EM78P5840N/41N/42N
8-Bit Microcontrollers
The following figure shows the TMRX block diagram.
Fosc 1:2 1:8 1:32 1:64
To PWM1IF
MUX TMR1X
reset Period Match
Comparator
T1P0 T1P1 T1EN
PRD1 Data Bus Data Bus
PRD2
T2P0 T2P1 T2EN
Comparator
Period Match
Fosc 1:2 1:8 1:32 1:64
TMR2X MUX
reset
To PWM2IF
*TMR1X = TMR1H + TMR1L; *TMR2X = TMR2H +TMR2L
Figure 7-9 TMRX Block Diagram
Where: Fosc: Input clock Prescaler (T1P0~T1P1 & 21P0~T2P1): Options of 1:2, 1:8, 1:32, and 1:64 are defined by TMRX. It is cleared when any type of reset occurs. TMR1X & TMR2X: Timer X register. TMRX is incremented until it matches with the value of PRDX, and then it is reset to "0". TMRX cannot be read. PRD1 & PRDX: PWM period register When defining TMRX, refer to the related registers for its operation as indicated in the prescaler register. Make sure that the PWMX bits are disabled if their related TMRXs are enabled. That is, Bit 6 of the PWMCON register must be set to "0." Related Control Registers (R5 PAGE3) of TMR1 and TMR2
Bit 7 PWM2E Bit 6 PWM1E Bit 5 T2EN Bit 4 T1EN Bit 3 T2P1 Bit 2 T2P0 Bit 1 T1P1 Bit 0 T1P0
Perform the Timer programming procedures as follows: 1) Load PRDX with the TIMER period 2) Enable the interrupt function by setting IOCF Page 0, if required 3) Load a desired value to PWMCON with the TMRX prescaler value, enable TMRX, and then, disable PWMX.
42 * Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.11 Oscillator
The EM78P5840N/41N/42N can be operated in three different oscillator modes; i.e., Crystal mode, IRC mode, and ERIC mode. The modes can be selected by setting the code option accordingly. The following sections describe in details the three oscillator modes.
7.11.1 Crystal Mode
To operate in Crystal mode, one crystal and two capacitors are needed for the external circuit. In this mode, the EM78P5840N/41N/42N can run in three active modes, i.e., Normal mode, Green mode, and Sleep mode. The advantages of Crystal mode opeation are low power consumption (in Green mode) and a more accurate main CLK. The following figure shows the Crystal mode application circuit. Pin XIN and Pin XOUT can be directly connected to a crystal to generate an oscillation. By clearing the code option "P70S" to "0," Port 70 will switch and operate as a general I/O (the PLL function must be disabled to prevent activating the Normal mode). The /RESET pin will switch to Port 71 if "P71S" is cleared to "0."
XIN
EM78P5840N
XOUT
Figure 7-10a Crystal Mode Application Circuit
Figure 6-10b Correlation between Normal, Green, and Sleep Modes in Crystal Mode Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 43
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.11.2 IRC Mode
For some applications where timing is not critical or where accurate oscillator frequencies are not required, using the RC oscillator offers a cost effective oscillator configuration. The EM78P5840N/41N/42N provides an internal RC mode with default frequency values of 4M and 2MHz. In IRC mode, the PLLC, XIN, XOUT, and /RESET pins can be defined as general purpose I/Os. The IRC oscillation frequency can vary with VDD, temperature and process variations. Internal RC Drift Rate (Ta=25C, VDD=5V 5%, VSS=0V)
Drift Rate Internal RC Frequency 4MHz 2MHz Temperature (-40 ~+85C) 5% 5% Voltage (2.3V~5.5V) 5% 5% Process 4% 4% Total 14% 14%
Note: Theoretical values are for reference only. Actual values may vary depending on the actual process.
In IRC mode, Port 60, Port 61, and Port 70 are defined as bidirectional I/O. By clearing P71S in the code option to "0," the /RESET pin can also be set as input pin (Port 71). In IRC mode, only two active modes are available, i.e., Normal and Sleep modes. See Figure 7-11b for more details.
7.11.3 ERIC Mode
In ERIC mode the device has an internal capacitor and an external resistor (connected to VDD). The internal capacitor functions as a temperature compensator. In order to obtain a more accurate frequency, a precise resistor is recommended. Note that the oscillation frequency of the RC oscillator can vary with VDD, temperatore and process variations. Moreover, the package type and the PCB layout can also affect the system frequency. In addition, the package type and the the PCB layout also affects the system frequency. The applicable frequencies are listed in the following table: ERIC Mode Frequency Deviation:
Internal C, External R 4MHz (R=51K) 2MHz (R=100K) Frequency Range 3.5M ~ 4.4M 1.8M ~ 2.2M
44 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
ERIC's oscillation frequency is based on the IRC2's CLK (determined by code option "IRC2S"). For example, if IRC2S = 0, then IRC2's oscillation frequency is 2MHz. The system CLK can then be changed by adjusting R. However, in this case, the system CLK will always be greater than 2M. That is to say, the system CLK can only be adjusted to between 2M and 6M. The following table shows the relation between the system oscillating CLK and the external resistor values.
VDD R ERIC EM78P5840
Figure 7-11a ERIC Mode Application Circuit
The relationship between the system oscillating CLK and the external resistor values:
Frequency (Hz) 6M 5M 4M 3.58M 2.1M External Resistor () 34K 41K 51K 57K 97K Operating Voltage (VDD) 3.0 ~5.5 V 2.8 ~5.5 V 2.5 ~5.5 V 2.2 ~5.5 V 2.2 ~5.5 V
In ERIC mode, only two active modes can be achieved, i.e., Normal and Sleep modes. See the following figure (Figure 6-11b) for more details.
Figure 7-11b Relationship between Normal and Sleep Modes in IRC and ERIC Modes Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 45
EM78P5840N/41N/42N
8-Bit Microcontrollers
7.12 Power-on Considerations
Any microcontroller is not guaranteed to function properly before the power supply stabilizes at its steady states. The EM78P5840N/41N/42N power-on reset voltage ranges from 1.6V ~ 2.0V. Depending on user's application, VDD must drop to below 1.6V and remains OFF for 10s before power can be switched on again. This will reset the EM78P5840N/41N/42N and allows it to work normally. The extra external reset circuit can work well if VDD can rise at a very fast speed (50ms or less). However, in most cases where critical applications are involved and due to unstable power on conditions, extra external devices are required to deal with the power-up concerns.
7.13 External Power-on Reset Circuit
By setting the code option "P71S" to 1, the /RESET pin is selected. The following figure shows how an external RC produces a reset pulse. The pulse width should be kept long enough for VDD to reach minimum operating voltage. The Diode D acts as a short circuit during power down. The Capacitor C will discharged rapidly and fully.
VDD R /RESET C D
Figure 7-12a External Power-on Reset Circuit 1
The POR reset voltage varies depending on the actual temperature or process variations. For some applications, a constant reset voltage is important. The following figure shows an example circuit that supports an adjusted reset voltage. By adjusting R41 and R46, POR reset voltage will be a constant (Vpor) and the potential voltage on the /RESET pin will drop to "0" when the VDD drops to below Vpor. The graph in Figure 7-12c shows the relation between VDD and Vpor. When R41=3.9M and R46=910K, /RESET will remain at "0" if VDD is below 2.24V, and is reactivated after VDD goes above 2.1V (see Figure 7-12c).
46 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
VDD
R41 3M9 3.9M R44
R42 2M2 2.2M
R43 330K RESET
22M Q3
Q2 C31 C1815 104 S10 RESET
R46 910K
C1815
Figure 6-12b External Power-on Reset Circuit 2
Figure 6-12c Relationship between VDD and Vpor
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 47
EM78P5840N/41N/42N
8-Bit Microcontrollers
8
Absolute Maximum Ratings
Rating
DC Supply Voltage Input Voltage Operating Temperature Range
Symbol
VDD Vin Ta
Value
-0.3 To 6 -0.5 to VDD +0.5 0 to 70
Unit
V V C
9
DC Electrical Characteristics
Ta = 25C, AVDD=VDD=5V5%, VSS=0V
Parameter Input leakage current for Input pins Input leakage current for bidirectional pins Input high voltage (except P71) Input low voltage (except P71) P71 Input high voltage P71 Input low voltage Input high threshold voltage Input low threshold voltage Clock input high voltage Clock input low voltage Output high voltage for Port C1~Port C2 Output high voltage for Port 60~Port 67; Port 7 Output high voltage for Port 9 Output low voltage for Port C1~Port C2 Output low voltage for Port 60~Port 67; Port 7 Output low voltage for Port 9 Pull-high current Power down current (Sleep mode) Low clock current (Green mode) Operating supply current (Normal mode) Symbol IIL1 IIL2 VIH VIL VIH VIL VIHT VILT VIHX VILX VOH1 VOH2 VOH3 VOL1 VOL2 VOL3 IPH ISB1 /RESET, TCC /RESET, TCC OSCI OSCI IOH = -6mA IOH = -10mA IOH = -15mA IOH = 6mA IOH = 10mA IOH = 15mA Pull-high active input pin at VSS All input and I/O pins at VDD, Output pin floating, WDT disabled CLK=32.768kHz, All analog circuits disabled, All input and I/O pinS at VDD, Output pin floating, WDT disabled /RESET=High, CLK=3.582MHz All analog circuits disabled, Output pin floating Condition VIN = VDD, VSS VIN = VDD, VSS Min 2.5 2.0 2.0 3.5 2.4 2.4 2.4 Typ -10 1 1.5 0.4 0.4 0.4 -15 4 0.8 0.8 0.8 Max Unit 1 1 A A V V V V V V V V V V V V V V A A
ISB2
-
25
35
A
ICC1
-
1.5
2.5
mA
48 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
9.1
Device Characteristic Graphics
The graphs below were derived based on a limited number of samples and they are provided for reference only. Hence, the device characteristic shown herein cannot be guaranteed as fully accurate. In these graphs, the data exceeding the specified operating range are shown for information purposes only. The device will operate properly only within the specified range.
IRC 2M and 4MHz OSC Frequency (VDD=3V) 6000 5000 Frequency (kHz) 4000 3000 2000 1000 0 -40 0 25 Temperature ()
Fig. 8-1 Internal RC OSC Frequency vs. Temperature, VDD=3V
70
85
F i g Fig. 8-2 Internal RC OSC Frequency vs. Temperature, VDD=5V * 49
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
10 AC Electrical Characteristics
CPU Instruction Timing (Ta = 25C, AVDD=VDD=5V, VSS=0V)
Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period *N = selected prescaler ratio Symbol Dclk Tins Tdrh Ttcc Twdt Condition 32.768kHz 3.582MHz Min 45 (Tins+20)/N 16-30% Typ 50 60 550 16 16 Max 55 16+30% Unit % s ns ms ns ms
*
Ta = 25C
ADC Characteristics (VDD = 5V, Ta = +25C, for Internal Reference Voltage)
Parameter Upper bound offset voltage Lower bound offset voltage Symbol Vofh Vofl Condition Min Typ 44 32 Max 52.8 38.4 Unit mV mV
These parameters are theoretical values and have not been tested. See Section 9.2, The Characteristics of EM78P5840N/41N/42N 10-bit ADC for further details.
Timing Characteristics (AVDD=VDD=5V,Ta=+25C)
Description Symbol Min Typ Max Unit
Oscillator Timing Characteristics Crystal start up 32.768kHz 3.579MHz PLL Tosc 400 5 1500 10 ms s
Timing Characteristics On Reset The minimum width of the reset low pulse The delay between reset and the start of the program Trst Tdrs 3 18 s ms
50 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
Figure 9-1 Relationship between OSC Stable Time and Power-on Reset
10.1 Operating Voltage vs Main CLK
Y axis: main CLK
MHz
14.3 3.58
V 2.2 3.6 5.5
X axis: min VDD
Figure 9-2 Relationship between Operating Voltage and the Main CLK
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 51
EM78P5840N/41N/42N
8-Bit Microcontrollers
10.2 10-Bit ADC Characteristics
The EM78P5840N/41N/42N has a built-in 10-bit resolution, multichannel ADC function. In an ideal situation, if ADC's reference voltage is 5V, the ADC's LSB is 5V/1024. However, due to some physical or circuit characteristics, the convertion result may be adversely affected. An example is shown in the next figure. The offset voltage reduces the AD's converter range. If the AD's input voltage is less than VOFL, the ADC will output a "0." On the other hand, if the input voltage is larger than (VDD-VOFH), the ADC will output 1023. That is , the AD converter range will be replaced by (VDD-VOFH+LSB-VOFL+LSB). If VRB = VOFL - LSB and VRT = VDD-VOFH+LSB, then LSB is: LSB = (VRT - VRB) / 1024 LSB = (VDD - (VOFH+VOFL) ) / 1022
NOTE During actual operation, carefully observe the resulting effect of the AD offset voltage. When the converter range is VRT ~ VRB, the AD converter's result will be more precised.
10-bit ADC
VDD VRT Min. input for ADC output = 1023 VOFH
(For 10-bit ADC, internally it takes this range to average 1024 steps)
Min. input for ADC output = 1 VOFL VRB 0V
Figure 9-3 Relationhip between ADC and Offset Voltage
52 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
11 Timing Diagrams
ins
Figure 10-1 AC Timing Diagrams
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 53
EM78P5840N/41N/42N
8-Bit Microcontrollers
12 OTP ROM Burning Pins
One time programmable ROM burning pins:
OTP Pin Name VDD VPP DINCK ACLK PGMB OEB DATA GND Mask ROM Pin Name AVDD /RESET P65 P64 P63 P62 P73 AVSS
54 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
Appendix
A Package Type
OTP MCU EM78P5840NM EM78P5840NP EM78P5841NM EM78P5841NP EM78P5842NM EM78P5842NP EM78P5842NK Package Type SOP DIP SOP DIP SOP DIP Skinny DIP Pin Count 18 pins 18 pins 20 pins 20 pins 24 pins 24 pins 24 pins Package Size 300mil 300mil 300mil 300mil 300mil 600mil 300mil
B Package Information
B.1 EM78P5840NM
Figure B-1a EM78P5840N 18-pin SOP Package Type
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 55
EM78P5840N/41N/42N
8-Bit Microcontrollers
B.2 EM78P5840NP
Figure B-1b EM78P5840NP 18-pin PDIP Package Type
B.3 EM78P5841NM
Figure B-2a EM78P5841NM 20-pin SOP Package Type
56 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
B.4 EM78P5841NP
Figure B-2b EM78P5841NP 20-pin PDIP Package Type
B.5 EM78P5842NM
Figure B-3a EM78P5842NM 24-pin SOP Package Type Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 57
EM78P5840N/41N/42N
8-Bit Microcontrollers
B.6 EM78P5842NP
Figure B-3b EM78P5842NP 24-pin PDIP Package Type
B.7 EM78P5842NK
Figure B-4a EM78P5842NK 24-pin Skinny DIP Package Type 58 * Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
C Numbering System EM78 P 5 8 4 0 N P
Package Type: P : PDIP, M : SOP, K : Skinny DIP Quality Level: Industrial Pin Count: 0 : 18-pin, 1 : 20-pin, 2 : 24pin ROM Type: P : OTP, R :ROMLESS, omitted :Mask
D EM78P5840N Series
D.1 EM78P5840N Series Category
ROMLESS ICE5840 OTP EM78P5840N EM78P5841N EM78P5842N Mask EM785840N EM785841N EM785842N
D.1.1 Differences between ICE5840, EM78P5840N and EM785840N
Item
CID RAM CID RAM Address Auto +1 CNT1* CNT2** Stack 8-bit counter
ICE5840
1024 byte
EM78P5840N Series
NA NA 8-bit counter x 8
EM785840N Series
NA NA 8 or 16 (shared with CNT2) bit counter
x
12
*
8
*CNT1 can be shared with CNT2 to generate a 16-bit counter under EM785840N/41N/42N. **CNT2 is NOT supported by ICE5840 and EM78P5840N/41N/42N.
D.2 EM78P5840N Series Package Type
EM78P5840N Series
EM78P5840NP EM78P5840NM EM78P5841NP EM78P5841NM EM78P5842NP EM78P5842NK EM78P5842NM
Package
18 pin PDIP 18 pin SOP 20 pin PDIP 20 pin SOP 24 pin PDIP 24 pin skinny DIP 24 pin SOP
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 59
EM78P5840N/41N/42N
8-Bit Microcontrollers
D.2.1 Differences between EM78P5840N, EM78P5841N, and EM78P5842N
Item
Pin Count PWM AD Channel IO (max.)
EM78P5840N
18 x 8 16
EM78P5841N
20 2 channels 8 18
EM78P5842N
24 2 channels 8 22
60 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
EM78P5840N/41N/42N
8-Bit Microcontrollers
E
Application Notes
1. There are some undefined or not existing bits in the registers. User needs to be cautious in dealing with those bits while programming and should not use them as data to execute logic or math operations, since those bits have no relative functions and have never been tested. Different symbols are used to distinguish them. "0" or "1" value always equal to 0 or value always equal to 1, (not existent, read only) "-" value unknown, (not existent) undefined bits are not allowed for use.
2. You will notice that most of the register bit number, name, type, etc., are shown in table format in this specification. The following are the conventions used to describe the entry in each row and column in the table.
RA PAGE0
Bit 7 RAB7 R/W-0 Bit type Bit name Bit number
Bit 6 RAB6 R/W-0
Bit 5 BAB5 R-1
Bit 4 RAB4 R/W-1
read/write (default value=1)
Bit 3 -
Bit 2 RAB2 R
Bit 1 RAB1 R-0
Bit 0 RAB0 R/W
read/write (w/o default value)
read/write (default value=0)
read only (w/o default value)
(undefined) not allowed to use read only (default value=1) read only (default value=0)
Register name and its page
3. Always set IOCC PAGE1 Bit 0 = 1, otherwise partial ADC function cannot be used. 4. Do NOT switch the MCU operation mode from Normal mode to Sleep mode directly. Before going into Idle or Sleep mode, switch the MCU to Green mode first. 5. While switching the main clock (regardless whether from high freq to low freq or vice versa), adding six instruction delay (NOP) is required. 6. The offset voltage will affect the ADC result. See Figure 10-3 in Section 10-2 for details. 7. Do NOT connect unnecessary circuits on the OTP burner pins during the burning process of the OTP ROM. 8. For low pin count package, some pins do not appear on package, but they exist on dies. Do NOT keep these unused pins floating. Set these pins output to high or low.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
* 61
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8-Bit Microcontrollers
62 *
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)

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